The use of micro-electromechanical systems (MEMS) and nano-electromechanical systems (NEMS) for ultrahigh density data storage has recently been reported. This approach to data storage utilizes a thermomechanical local probe technique with large arrays of nanometer-scale tips, such as are now used in atomic-force microscope and scanning-tunneling microscope technology. In this technique, a read/write operation is performed by heating a cantilever mechanism, causing a tip to contact a thin film storage medium and either create or detect depressions made therein. Some details of the design of MEMS structures for data storage have been recently published in IBM J. Res. Develop. 44, 323 (2000) and in Sensors and Actuators 80, 100 (2000).
An individual cantilever cell is shown schematically in FIG. 1A (cross-section view) and FIG. 1B (plan view). The MEMS chip 1, typically of silicon, is processed to yield a silicon cantilever 10 with a tip 11 and a heater 13. As shown in FIG. 1A, the cantilever structure 10 is formed on a layer at the surface of chip 1, and a cavity is then etched in the bulk silicon behind cantilever 10. Applying electrical power via the through connection 15 causes a temperature increase in the heater and tip, which is in contact with storage medium 12 (typically a thin polymer film on a silicon substrate). The combination of tip pressure on the storage medium and the tip heating causes the tip to create an indentation in the storage medium, thereby realizing thermomechanical data writing with very high bit areal densities.
A conventional 2-dimensional arrangement for controlling the MEMS chip 1 is shown schematically in FIG. 2. The MEMS chip 1, which includes a large number of individual cells, is electrically controlled by multiplex drivers 2 having conventional wirebonding connections to the edge of chip 1. There are limitations inherent in the 2-dimensional arrangement of electrical connections. For example, as the number of cells in chip 1 increases, it becomes more difficult to provide electrical isolation between cells; at the same time, higher power is required to address the cell array while the size of individual connections decreases.
Accordingly, there is a need for a 3-dimensional integration scheme in which MEMS devices and their control devices (such as CMOS logic chips) may be interconnected, in order to overcome the electrical limitations of the conventional 2-dimensional configuration.